A single project crossed every timeline this week, wrapped in the kind of language that should make an operator slow down rather than speed up. The honest version is more interesting than the viral one. A transformer was implemented as a physical circuit, gate by gate, and it works. It is also a 4,192-parameter teaching model spelling names on a small screen. Both things are true, and the gap between them is the lesson.
A full transformer, designed gate by gate
Fabio Guzman took Andrej Karpathy's microGPT — a character-level model with one transformer block, four attention heads, a 24-dimension embedding and a 16-token context — and implemented it directly in hardware description language, then ran it on a Xilinx Virtex-5 FPGA. No GPU, no CPU, no software inference loop. The arithmetic is the circuit.
The numbers he reports are real and worth stating precisely: roughly 50,000 to 69,000 tokens per second at 80 MHz, in Q5.11 fixed-point, across about 0.45 million gate-equivalents. A persistent KV cache — computing only the new token's keys and values each step instead of recomputing the window — was the single largest win, worth about 3.2x. As an exercise in taste and discipline it is excellent engineering, and the author is clear that it is a demonstration: a board generating names on an LCD, not a product.
Read the number in context
The framing travelling around — burned into silicon, less energy than a calculator, will scale to far larger models — is where the care is needed. A separate benchmark by Alex Cheema runs the same microGPT five ways and finds that a single MacBook P-core in tuned C does on the order of 71x the FPGA's throughput. The model is so small that the measurement mostly captures dispatch overhead, not silicon prowess; even NumPy and a GPU path come in slower for the same reason.
The FPGA's genuine advantage is roughly two watts and deterministic latency in a small form factor, not raw speed. "Scales to far larger models" is asserted, not demonstrated.
This matters because the leap from a 4,192-parameter character model to a useful language model is not a matter of adding gates. It is memory bandwidth, weight storage, numerical range and the cost of fabricating fixed silicon for a model that changes every quarter. None of that is on display here, and saying so is not a knock on the work.
Why an operator should still care
The durable signal is not this board. It is the direction it gestures at: when a workload is fixed and known, you can specialise the hardware to it and stop paying the general-purpose tax. That is a real industry bet, not a hobby one — it is the thesis behind transformer-specific silicon such as Etched's Sohu ASIC, which raised on exactly this premise. For anyone weighing edge and on-device inference, the questions worth holding are determinism, power envelope and form factor — the axes where dedicated silicon wins — rather than headline tokens per second.
The through-line for a senior team: treat the demo as a proof of taste, not a scaling claim, and treat the reshares as a reminder to read the primary source. The engineering deserves respect. The economics of replacing your inference stack with custom silicon are not settled by a chip that spells names. Knowing the difference is the entire job.